In a typical active matrix display each pixel is provided with a transistor, more particularly a thin film field effect transistor (TFT, FET) which is used to control the appearance of the pixel. Broadly speaking, the gate connection of the FET is connected to a select line to select the pixel for writing data, and one of the source and drain of the FET is connected to a data line for writing data to the pixel, the other being connected to a pixel electrode for driving the display medium. In some types of display, for example, electronic paper displays such as electrophoretic displays, the pixel electrodes are located on one face of the display medium and a common electrode is provided covering the opposite face of the display medium thereby enabling an electric field to be provided across the display medium, for example to switch the device from one display state, say white, to another say black (or vice versa). The skilled person will appreciate that pixel circuits may in practice be more complex than this, but the same general features remain.
One problem in such displays is parasitic capacitance between the gate and pixel electrodes; in an electrophoretic display this can be exacerbated by the presence of the common pixel electrode, which is used to provide a bigger pixel capacitance. Active matrix displays, where the pixel voltage or current is controlled by one or more thin film field effect transistors, dominate electronic display design. In, say, a top-gate transistor TFT (either a top-gate or a bottom-gate configuration may be employed) the gate electrode needs to overlap with the semiconducting channel and the overlap regions between the gate electrode and the source and drain electrodes determine the parasitic gate-source and gate-drain overlap capacitance Cgs and Cgd, respectively.
These should generally be as small as possible to improve the switching speed of the TFTs and minimize unwanted capacitive coupling effects. In an active matrix display Cgs is particularly important as it determines the capacitive coupling between the signals running along the gate lines and the pixel electrode. When the gate voltage is switched to turn off the TFT at the end of a particular addressing (pixel charging) cycle Cgs causes the voltage on the pixel to tend to follow the switching of the gate voltage. This so-called kickback voltage offsets the pixel voltage from the intended value to which the pixel had been charged with the signal on the data line, and has a deleterious effect on the visual appearance of the display. This problem with parasitic capacitance becomes important when Cgs is large and the problem is particularly acute with flexible substrates, such as plastic substrates because plastic substrates exhibit significant dimensional changes when subject to mechanical stress or temperature variations both of which occur during any manufacturing process. Further, by comparison with structures on silicon or glass, thin film transistors (TFTs) on a plastic substrate tend to be physically larger and to thus exhibit a larger capacitance.
A pixel capacitor can be used to reduce the effect of the parasitic overlap capacitance as the kickback voltage induced on the pixel electrode by the switching gate voltage is smaller the larger the capacitance of the pixel electrode is. The display medium itself has a capacitance so that a pixel capacitor may comprise capacitance between a pixel electrode (source or drain electrode of a pixel drive TFT) and a pixel capacitor counter electrode, which may simply comprise a common electrode extending over a (front) surface of the display (the backplane being on the display rear surface). Thus the common pixel electrode may be a substantially transparent electrode on the viewing surface side of the display.
Pixel capacitors are particularly important when used in conjunction with thicker display media such as electronic paper where the thickness of the display effect, such as an electrophoretic media, leads to a lower capacitance of the display element itself. In these displays the pixel capacitor can take up a significant fraction of the pixel, especially where the kickback effect is large. For example, in our patent application WO2009/133388 (US2011/010361) we have described how an off-set pixel electrode can be used to achieve increased storage capacitance. In such an off-set configuration the top pixel electrode is deposited to overlap the first capacitor plate (COM electrode) of one device and also the gate electrode of a neighbouring device.
Referring to FIG. 1a, this shows a vertical cross-section (along a staggered line) through an example of such an active matrix backplane structure. In FIG. 2a a substrate 1 bears a thin film transistor (TFT) device comprising source and drain electrodes 2,3, a layer of semiconducting material 4, a gate dielectric 5 and a gate electrode/interconnect 6. A COM electrode 7 is formed in the same later as gate electrode 6. An upper dielectric 8 overlies the gate and COM electrodes and a top pixel electrode 12 is provided over dielectric layer 8, connected to one of the source/drain electrodes by a via 9. FIG. 1b shows the structure from above, illustrating that the COM electrode is patterned to provide a non-conducting cut-away for via 9. The top pixel electrode overlaps with the COM electrode (Cn) 7 of the first device (Device 1) and the gate electrode (Gn+1) of the neighbouring device (Device 2).
Storage capacitance CStorage is obtained from an overlap between the COM electrode and the drain electrode. The effect of an off-set top pixel electrode is an increase in overall storage capacitance caused by an overlap between the top pixel electrode and the COM electrode as well as between the top pixel electrode and the gate (Gn-1). The parasitic capacitance between the gate electrode and the drain electrode remains unchanged but the parasitic capacitance between the top pixel electrode and the gate electrode decreases and thus the storage capacitance (Cstorage) may be increased by lowering the top pixel dielectric thickness. This increases the overall CStorage/CParasitic capacitance ratio, thus increasing overall pixel capacitance and reducing kickback voltage and variation. The top pixel dielectric layer may be tuned to maximise Cstorage, without increasing Cparasitic.
We have previously described techniques to address the problems of gate kickback, for example in our PCT/GB2012/050813. There are, however, other problems which are not easy to understand. For example, particularly when using an organic TFT (thin film transistor) backplane on a flexible, plastic substrate some regions of a non-volatile (electronic paper) display can end up darker than others after the backplane has been powered down.